Topical Workshop: FPGAs in Research - Applications, Technologies and Tools

High Level Synthesis with Xilinx HLS

Dec 4, 2012, 9:00 AM

1h 30m

Room 110 in Building 2.5 (Zentralinstitut für Elektronik, Forschungszentrum Jülich)

Invited Talk

Speaker

Mr Eugen Krassin (plc2)

Description

Agenda Functional Abstraction Level High Level Synthesis HLS Control & Datapath Extraction Scheduling & Binding Arbitrary Precision Data Types Top Level I/O Ports Loops Arrays Interfaces First Example Latency & Throughput Optimizations

Presentation materials

Slides

juelich_hls.pptx