Bjoern Spruck
(Uni Gießen)
12/3/12, 3:45 PM
In this talk we present the Compute Node, an ATCA carrier board and AMC board design based on Virtex-4 FX60 and Virtex-5 FX70T FPGAs.
The system is designed to perform data acquisition of 22 GB/s and data reduction by a factor <10 at the Belle II pixel detector,
which is supposed to start operation in 08/2015. The firmware programming comprises buffer management with pointer lookup...
Simone Esch
(Forschungszentrum Jüich)
12/3/12, 4:10 PM
The $\overline{\text{P}}$anda detector is one of the main experiments at the upcoming Facility for Antiproton and Ion Research in Darmstadt (FAIR). The fixed target experiment will explore $\overline{\text{p}}$p annihilation with intense, phase space cooled beams with momenta between 1.5 and 15 GeV/c.
For the development of the Micro Vertex Detector (MVD), the innermost tracking detector of...
Michael Schnell
(University of Bonn)
12/3/12, 4:35 PM
The innermost two layers of the Belle II detector located at the KEK facility in Tsukuba, Japan, will be covered by high granularity DEPFET pixel (PXD) sensors. This leads to a high data rate of around 60 Gbps, which has to be significantly reduced by the Data Acquisition System. For the data reduction the hit information of the surrounding silicon strip detector (SVD) is used to define...
Mr
Marius Wensing
(Bergische Universität Wuppertal)
12/3/12, 5:00 PM
Für das Upgrade des ATLAS Pixel-Detektors am Large-Hadron-Collider ist ein Neudesign der Datenauslese notwendig. Im Insertable b-Layer werden 448 zusätzliche Front-End-Chips verbaut, für deren Auslese neue FPGA-Auslesekarten bestehend aus Back-of-Crate- (BOC) und Read-Out-Driver-Karte (ROD) entwickelt worden sind. Der Vortrag beschäftigt sich mit der Firmware-Entwicklung und den ersten...
