Forschungszentrum Jülich: FPGAs in Research - Applications, Technologies and Tools (3-4 December 2012)

Forschungszentrum Jülich: FPGAs in Research - Applications, Technologies and Tools

from Monday, 3 December 2012 (12:00) to Tuesday, 4 December 2012 (16:00)

Monday, 3 December 2012

12:00 Lunch
Lunch
12:00 - 13:00
Room: Room 110 in Building 2.5
13:00
13:00 - 15:15
Room: Room 110 in Building 2.5
Contributions

13:00 Introduction - Harald Kleines (Forschungszentrum Jülich)

13:05 Zentralinstitut für Elektronik - Facts, Figures, Tasks & Topics - Harald Kleines (Forschungszentrum Jülich)

13:20 FPGA-basierte digitale Gamma-Spektroskopie zur Überwachung der Umweltradioaktivität - Markus Dambacher (FMF)

14:00 FPGA-based Tomographiecameras - Jörg Burmester (HZG) Jörn Plewka (HZG)

14:25 FPGA-based algorithm for center of gravity calculation of clustered signals using RAM for history storing - Andriy Ushakov (Helmholtz zentrum Berlin)

14:50 Development of a FPGA based DAQ for digital SiPM‘s using USB 3.0 - Holger Noeldgen (Forschungszentrum Juelich)
15:15 Coffee Break
Coffee Break
15:15 - 15:45
Room: Room 110 in Building 2.5
15:45
15:45 - 17:25
Room: Room 110 in Building 2.5
Contributions

15:45 The ATCA based Compute Node and its application in the Belle II PXD-DAQ - Bjoern Spruck (Uni Gießen)

16:10 The Juelich Digital Readout System for $\overline{\text{P}}$anda development - Simone Esch (Forschungszentrum Jüich)

16:35 Data Concentrator for the Belle II DEPFET Pixel Detector - Michael Schnell (University of Bonn)

17:00 Firmware-Entwicklung für die ATLAS IBL BOC Karte - Marius Wensing (Bergische Universität Wuppertal)
19:00 Dinner
Dinner
19:00 - 22:00
Room: Große Rurstraße 94
Tuesday, 4 December 2012
09:00
09:00 - 10:30
Room: Room 110 in Building 2.5
Contributions

09:00 High Level Synthesis with Xilinx HLS - Eugen Krassin (plc2)
10:30 Coffee Break
Coffee Break
10:30 - 11:00
Room: Room 110 in Building 2.5
11:00
11:00 - 12:15
Room: Room 110 in Building 2.5
Contributions

11:00 FPGA Programming Methods - An Overview - Diana Goehringer (KIT)

11:25 Matlab/Simulink and HDL-coder - Renhai Xiong (Forschungszentrum Jülich)

11:50 Parallelisation potential of image segmentation in hierarchical island structures on hardware-accelerated platforms in real-time applications - Sergey Suslov (Research Center Juelich, Central Institute for Electronics)
12:15 Lunch
Lunch
12:15 - 13:15
Room: Room 110 in Building 2.5
13:15
13:15 - 15:20
Room: Room 110 in Building 2.5
Contributions

13:15 Field Programmable Gate Array Based Data Digitisation with Commercial Elements - Cahit Ugur (GSI)

13:40 An FPGA Platform for Ultra-fast Data Acquisition - Michele Caselle (KIT)

14:05 FPGA Oriented HW/FW Development in FEA DESY - Frantisek krivan (DESY)

14:30 FPGA- Framework development for a MicroTCA system - Qingqing Xia (DESY)

14:55 Dynamische Re -Konfiguration eines FPGAs mittels internem Kontroller - Markus Dick (Forschungszentrum Juelich)