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Description
(3) Results
Table 1 summarizes the key technical features of the designed platform that we expected. Schematic design and PCB circuit design of the boards in the front-end subsystem have been almost completed, the hardware circuit debugging will be finish in three months. The performance of the data transmission and storage subsystem have been test. The sequential write can be up to 5000MB/S, greater than the maximum theoretical data rate of the front-end subsystem.
(4) Discussion and Conclusion
The designed platform will be helpful for the algorithm research.
(2) Material and Methods
The system architecture of the platform is shown in Fig. 1. The platform consists of a front-end subsystem and a data transmission and storage subsystem. Excitation, channel selection, signal digitization and data packing is done by the front-end subsystem. Data transmission, sequencing, storage and processing is done by the data transmission and storage subsystem.