Oct 19 – 20, 2016
HZDR
Europe/Berlin timezone

FPGA: 10Gb/s IP (KIT)

Oct 20, 2016, 9:30 AM
30m
HZDR

HZDR

Zentralabteilung Forschungstechnik Helmholtz-Zentrum Dresden-Rossendorf e.V. Sekretariat Bautzner Landstraße 400 01328 Dresden

Speaker

Denis Tcherniakhovski

Presentation materials

There are no materials yet.